Data communication in parallel architectures
type: Item
instance of: scholarly article
title: Data communication in parallel architectures
zbMATH Open document ID: 0681.68007
DOI: 10.1016/0167-8191(89)90024-0
author: Y. Saad
author: Martin H. Schultz
published in: Parallel Computing
publication date: 1989-01-01T00:00:00Z
review text: Timing estimates for various forms of data exchange in a variety of parallel architectures are investigated. Data exchange methods emphasized are: one to one, one to all, all to all, scatter, and multiscatter. Parallel architectures, emphasized are: bus, shared memory, ring, grid, hypercube and switch. Tables summarizing the timing estimates are given.
Mathematics Subject Classification ID: 68N99
Mathematics Subject Classification ID: 68N25
zbMATH DE Number: 4115916
zbMATH Keywords: parallel computer
zbMATH Keywords: interprocessor communication
zbMATH Keywords: Data exchange
MaRDI profile type: Publication
full work available at URL: 0167-8191(89)90024-0
OpenAlex ID: W2036341441
description: scientific article; zbMATH DE number 4115916