Integrating side channel security in the FPGA hardware design flow
type: Item
instance of: scholarly article
title: Integrating side channel security in the FPGA hardware design flow
DOI: 10.1007/978-3-030-68773-1_13
author: Alessandro Barenghi
author: Matteo Brevi
author: William Fornaciari
author: Gerardo Pelosi
author: Davide Zoni
publication date: 2022-12-16T00:00:00Z
Mathematics Subject Classification ID: 68-XX
Mathematics Subject Classification ID: 94A60
zbMATH DE Number: 7633697
zbMATH Keywords: design automation and tools
zbMATH Keywords: FPGA design flow
zbMATH Keywords: side channel analysis
cites work: Trace-based schedulability analysis to enhance passive side-channel attack resilience of embedded software
cites work: Mutual information analysis: a comprehensive study
cites work: Q4536295
cites work: A Design Flow and Evaluation Framework for DPA-Resistant Instruction Set Extensions
cites work: GitHub
describes a project that uses: Yosys
describes a project that uses: SymbiFlow
describes a project that uses: GitHub
MaRDI profile type: Publication
full work available at URL: 978-3-030-68773-1 13
OpenAlex ID: W3127222271
description: scientific article; zbMATH DE number 7633697