Q3435076
type: Item
instance of: scholarly article
zbMATH Open document ID: 1138.94402
author: Josef Strnadel
publication date: 2007-05-04T00:00:00Z
Mathematics Subject Classification ID: 94C12
Mathematics Subject Classification ID: 94C15
zbMATH DE Number: 5149341
zbMATH Keywords: digital circuit
zbMATH Keywords: testing
zbMATH Keywords: register-transfer level
zbMATH Keywords: data-path
zbMATH Keywords: testability analysis
zbMATH Keywords: design for testability
zbMATH Keywords: scan technique
MaRDI profile type: Publication
Recommended article: Methods of testability analysis for digital logic
Recommended article: Development of tests for VLSI circuit testability at the upper design levels
Recommended article: Analysis of signature testability of digital circuits
Recommended article: Q3126256
Recommended article: On the testability of iterative logic arrays
Recommended article: Testing of register data transfer control mechanisms in microprocessors
Recommended article: Q4025671
description: scientific article