PSP: parallel sub-pipelined architecture for high throughput AES on FPGA and ASIC
type: Item
instance of: scholarly article
title: PSP: parallel sub-pipelined architecture for high throughput AES on FPGA and ASIC
zbMATH Open document ID: 1409.94902
published in: Central European Journal of Computer Science
publication date: 2014-11-10T00:00:00Z
Mathematics Subject Classification ID: 94A60
zbMATH DE Number: 6367282
zbMATH Keywords: cryptography
zbMATH Keywords: AES
zbMATH Keywords: FPGA
zbMATH Keywords: ASIC
zbMATH Keywords: parallel sub-pipelined
zbMATH Keywords: throughput
MaRDI profile type: Publication
full work available at URL: s13537-013-0112-2
OpenAlex ID: W2034282686
cites work: Cryptanalysis of Block Ciphers with Overdefined Systems of Equations
cites work: Q3374924
cites work: Q4941844
cites work: Key Recovery Attacks of Practical Complexity on AES-256 Variants with up to 10 Rounds
DOI: 10.2478/S13537-013-0112-2
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author: K. Rahimunnisa
author: P. Karthigaikumar
author: N. Anitha Christy
author: S. Suresh Kumar
author: J. Jayakumar
description: scientific article; zbMATH DE number 6367282