Efficient arithmetic in garbled circuits
type: Item
instance of: scholarly article
title: Efficient arithmetic in garbled circuits
DOI: 10.1007/978-3-031-58740-5_1
author: David G. Heath
publication date: 2024-11-13T00:00:00Z
Mathematics Subject Classification ID: 68-XX
zbMATH DE Number: 7943456
zbMATH Keywords: garbled circuits
zbMATH Keywords: arithmetic circuits
MaRDI profile type: Publication
cites work: How to Garble Arithmetic Circuits
cites work: New ways to garble arithmetic circuits
cites work: Q4035736
cites work: On the Security of the “Free-XOR” Technique
cites work: Arithmetic garbling from bilinear maps
cites work: Fast garbling of circuits under standard assumptions
cites work: Half-tree: halving the cost of tree expansion in COT and DPF
cites work: Integer multiplication in time \(O(n\log n)\)
cites work: Tri-state circuits. A circuit model that captures RAM
cites work: FleXOR: Flexible Garbling for XOR Gates That Beats Free-XOR
cites work: Improved Garbled Circuit: Free XOR Gates and Applications
cites work: How to Garble RAM Programs?
cites work: Secure Two-Party Computation Is Practical
cites work: Three halves make a whole? Beating the half-gates lower bound for garbled circuits
cites work: Two Halves Make a Whole
description: scientific article; zbMATH DE number 7943456