Area-time tradeoffs for universal VLSI circuits
type: Item
instance of: scholarly article
title: Area-time tradeoffs for universal VLSI circuits
zbMATH Open document ID: 1157.68020
author: Sandeep Bhatt
author: Gianfranco Bilardi
author: Geppino Pucci
published in: Theoretical Computer Science
publication date: 2008-12-12T00:00:00Z
Mathematics Subject Classification ID: 68M99
zbMATH DE Number: 5382270
zbMATH Keywords: VLSI theory
zbMATH Keywords: area-universal networks
zbMATH Keywords: interconnection networks
MaRDI profile type: Publication
full work available at URL: j.tcs.2008.08.005
OpenAlex ID: W2017830172
cites work: Deterministic on-line routing on area-universal networks
cites work: Randomized Routing and Sorting on Fixed-Connection Networks
cites work: A lower bound for area-universal graphs
cites work: Efficient Simulations among Several Models of Parallel Computers
cites work: Optimal Rearrangeable Multistage Connecting Networks
cites work: A framework for solving VLSI graph layout problems
cites work: Q3997942
DOI: 10.1016/J.TCS.2008.08.005
description: scientific article; zbMATH DE number 5382270