Pages that link to "Item:Q1182347"
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The following pages link to Delay-time modelling and critical-path verification for CMOS digital designs (Q1182347):
Displaying 2 items.
- Integrated circuit design. Power and timing modeling, optimization and simulation. 12th international workshop, PATMOS 2002, Seville, Spain, September 11--13, 2002. Proceedings. (Q1881180) (← links)
- Simple and accurate modeling of the output transition time in nanometer CMOS gates (Q3075931) (← links)