Pages that link to "Item:Q1818690"
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The following pages link to On the speedup required for combined input- and output-queued switching (Q1818690):
Displaying 13 items.
- Performance analysis of clock-regulated queues with output multiplexing in three different 2x2 crossbar switch architectures (Q1200161) (← links)
- On iterative solutions for performance of high-speed switching networks (Q1301519) (← links)
- Anchored opportunity queueing: a low-latency scheduler for fair arbitration among virtual channels. (Q1426223) (← links)
- Port partitioning and dynamic queueing for IP forwarding (Q1603314) (← links)
- Costly circuits, submodular schedules and approximate Carathéodory theorems (Q1649974) (← links)
- Exact emulation of a priority queue with a switch and delay lines (Q2432273) (← links)
- Scheduling of an input-queued switch to achieve maximal throughput (Q2709777) (← links)
- Fast ping-pong arbitration for input-output queued packet switches (Q2762330) (← links)
- On Queue-Size Scaling for Input-Queued Switches (Q2956539) (← links)
- (Q3044910) (← links)
- Performance of trunk grouping in packet switch design (Q3994063) (← links)
- Synchronous versus asynchronous operation of a packet switch with combined input and output queueing (Q4022639) (← links)
- Stochastic comparison results for non-blocking switches with output queueing (Q4237929) (← links)