Pages that link to "Item:Q1953829"
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The following pages link to Cluster-based topologies for 3D Networks-on-Chip using advanced inter-layer bus architecture (Q1953829):
Displaying 4 items.
- Developing a power-efficient and low-cost 3D NoC using smart GALS-based vertical channels (Q1953823) (← links)
- Networks-on-Chip in a Three-Dimensional Environment: A Performance Evaluation (Q4975030) (← links)
- (Q5211841) (← links)
- Computing the Optimal Longest Queue Length in Torus Networks (Q6488368) (← links)
