Pages that link to "Item:Q2489272"
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The following pages link to Design and performance of a pixel-level pipelined-parallel architecture for high speed wavelet-based image compression (Q2489272):
Displaying 7 items.
- Low-delay parallel architecture for fractal image compression (Q308069) (← links)
- Haar wavelet based processor scheme for image coding with low circuit complexity (Q869332) (← links)
- An integrated systolic array design for video compression (Q1405480) (← links)
- VHDL implementation of the fast wavelet transform (Q2432138) (← links)
- Efficient FPGA architecture of optimized Haar wavelet transform for image and video processing applications (Q2658624) (← links)
- Parallel, pipelined and folded architectures for computation of 1-D and 2-D DCT in image and video codec (Q5947745) (← links)
- Scalable linear array architecture with data-driven control for ultrahigh-speed vector quantization (Q5947747) (← links)
