The following pages link to Keshab K. Parhi (Q1584048):
Displaying 44 items.
- (Q1405467) (redirect page) (← links)
- Digit-serial complex-number multipliers on FPGAs (Q1405468) (← links)
- A low power correlator for CDMA wireless systems (Q1405534) (← links)
- Relaxed annihilation-reordering look-ahead QRD-RLS adaptive filters (Q1405535) (← links)
- Power efficient folding of pipelined LMS adaptive filters with applications to wireline digital communications (Q1584049) (← links)
- P-CORDIC: A precomputation based rotation CORDIC algorithm (Q1773586) (← links)
- Frequency spectrum based low-area low-power parallel FIR filter design (Q1773588) (← links)
- Interleaved convolutional code and its Viterbi decoder architecture (Q1773676) (← links)
- Low-complexity decoding of block turbo-coded system with antenna diversity (Q1773677) (← links)
- Evaluation of CORDIC algorithms for FPGA design (Q1851098) (← links)
- Performance-scalable array architectures for modular multiplication (Q1851147) (← links)
- An FPGA implementation of \((3,6)\)-regular low-density parity-check code decoder (Q1886906) (← links)
- Hardware efficient fast computation of the discrete Fourier transform (Q2432132) (← links)
- Interleaved trellis coded modulation and decoder optimizations for 10 gigabit ethernet over copper (Q2432134) (← links)
- Models for architectural power and power grid noise analysis on data bus (Q2505077) (← links)
- On the performance and implementation issues of interleaved single parity check turbo product codes (Q2574066) (← links)
- Pipeline interleaving and parallelism in recursive digital filters. I. Pipelining using scattered look-ahead and decomposition (Q3202961) (← links)
- Pipeline interleaving and parallelism in recursive digital filters. II. Pipelined incremental block filtering (Q3202962) (← links)
- A pipelined adaptive lattice filter architecture (Q4202422) (← links)
- Parallel adaptive decision feedback equalizers (Q4202431) (← links)
- Design of data format converters using two-dimensional register allocation (Q4220999) (← links)
- A pipelined adaptive differential vector quantizer for low-power speech coding applications (Q4277132) (← links)
- Generalized multiplication-free arithmetic codes (Q4361497) (← links)
- A fast radix-4 division algorithm and its architecture (Q4419723) (← links)
- Pipelined Parallel Decision-Feedback Decoders for High-Speed Ethernet Over Copper (Q4564367) (← links)
- High-Speed VLSI Implementation of 2-D Discrete Wavelet Transform (Q4567638) (← links)
- A Low-Complexity Hybrid LDPC Code Encoder for IEEE 802.3an (10GBase-T) Ethernet (Q4569923) (← links)
- Systematic design of original and modified Mastrovito multipliers for general irreducible polynomials (Q4571336) (← links)
- High-Speed Parallel Architectures for Linear Feedback Shift Registers (Q4573199) (← links)
- Low-Latency Sequential and Overlapped Architectures for Successive Cancellation Polar Decoder (Q4578525) (← links)
- Early Stopping Criteria for Energy-Efficient Low-Latency Belief-Propagation Polar Code Decoders (Q4579635) (← links)
- Hardware Efficient Fast DCT Based on Novel Cyclic Convolution Structures (Q4588038) (← links)
- Low-Cost Fast VLSI Algorithm for Discrete Fourier Transform (Q4590168) (← links)
- Overlapped Message Passing for Quasi-Cyclic Low-Density Parity Check Codes (Q4590284) (← links)
- Hardware Efficient Fast Parallel FIR Filter Structures Based on Iterated Short Convolution (Q4590296) (← links)
- Low- Cost Parallel FIR Filter Structures With 2-Stage Parallelism (Q4590335) (← links)
- Architectures for Recursive Digital Filters Using Stochastic Computing (Q4622057) (← links)
- (Q5008332) (← links)
- FFT Architectures for Real-Valued Signals Based on Radix-$2^{3}$ and Radix-$2^{4}$ Algorithms (Q5008643) (← links)
- A Network-Efficient Nonbinary QC-LDPC Decoder Architecture (Q5008828) (← links)
- Low-Latency Low-Complexity Architectures for Viterbi Decoders (Q5010822) (← links)
- A Pipelined FFT Architecture for Real-Valued Signals (Q5010862) (← links)
- Probabilistic Spherical Detection and VLSI Implementation for Multiple-Antenna Systems (Q5010888) (← links)
- Joint<tex>$(3, k)$</tex>-Regular LDPC Code and Decoder/Encoder Design (Q5354071) (← links)
