Pages that link to "Item:Q2465512"
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The following pages link to Low-power, low-complexity bit-serial VLSI architecture for 1D discrete wavelet transform (Q2465512):
Displaying 9 items.
- Implementing single-scale wavelet transform processor with magnetostatic surface wave device (Q412986) (← links)
- Low power synthesis methodology with data format optimization applied on a DWT (Q1405544) (← links)
- VLSI architecture for forward discrete wavelet transform based on B-spline factorization (Q2508509) (← links)
- Efficient FPGA architecture of optimized Haar wavelet transform for image and video processing applications (Q2658624) (← links)
- Low complexity reconfigurable architecture for the 5/3 and 9/7 discrete wavelet transform (Q3642725) (← links)
- Design of New Optimized Architecture Processor for DWT (Q4798219) (← links)
- VLSI Implementation of Discrete Wavelet Transform for Lossless Compression of Medical Images (Q4800620) (← links)
- Bit-level systolic implementation of discrete orthogonal transforms (Q5958666) (← links)
- A low power \(8\times 8\) direct 2-D DCT chip design (Q5960766) (← links)
