Low-power, low-complexity bit-serial VLSI architecture for 1D discrete wavelet transform (Q2465512)
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scientific article
| Language | Label | Description | Also known as |
|---|---|---|---|
| English | Low-power, low-complexity bit-serial VLSI architecture for 1D discrete wavelet transform |
scientific article |
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Low-power, low-complexity bit-serial VLSI architecture for 1D discrete wavelet transform (English)
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4 January 2008
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The authors use the discrete wavelet transform (DWT) technique to propose a low complexity, low power bit-serial DWT architecture, employing a two channel lattice based quadrature mirror filter. ``The proposed architecture has several advantages over the existing DWT architecture'' tell the authors.
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bit-serial
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VLSI architecture
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folded architecture
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lattice-based FIR filters
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low complexity
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0.9398708
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0.9121833
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0.9019759
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0.9010154
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0.8836829
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0.87116766
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