Pages that link to "Item:Q4590345"

The following pages link to FPGA design and implementation of a low-power systolic array-based adaptive Viterbi decoder (Q4590345):

Displaying 2 items.

• VLSI architecture and implementation for FS1016 CELP decoder with reduced power and memory requirements (Q3840919) (← links)
• An Approach for Adaptively Approximating the Viterbi Algorithm to Reduce Power Consumption While Decoding Convolutional Codes (Q5356887) (← links)