Pages that link to "Item:Q5316691"
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The following pages link to Advanced Encryption Standard – AES (Q5316691):
Displaying 15 items.
- PSP: parallel sub-pipelined architecture for high throughput AES on FPGA and ASIC (Q469056) (← links)
- Glitch and laser fault attacks onto a secure AES implementation on a SRAM-based FPGA (Q656510) (← links)
- Resource efficient implementation of \(T\)-boxes in AES on virtex-5 FPGA (Q656579) (← links)
- Efficient hardware architecture for the AES-CCM protocol of the IEEE 802.11i standard (Q974167) (← links)
- Looting the LUTs: FPGA optimization of AES and AES-like ciphers for authenticated encryption (Q1746847) (← links)
- Efficient cryptography on the RISC-V architecture (Q2284120) (← links)
- Intel’s New AES Instructions for Enhanced Performance and Security (Q3391562) (← links)
- Ultra-Lightweight Implementations for Smart Devices – Security for 1000 Gate Equivalents (Q3537404) (← links)
- (Q4536214) (← links)
- Architectures and VLSI implementations of the AES-Proposal Rijndael (Q4571240) (← links)
- (Q4786104) (← links)
- Efficient Vector Implementations of AES-Based Designs: A Case Study and New Implemenations for Grøstl (Q4910237) (← links)
- Performance and Security Evaluation of AES S-Box-Based Glitch PUFs on FPGAs (Q4910847) (← links)
- Very Short Critical Path Implementation of AES with Direct Logic Gates (Q4912402) (← links)
- Ensuring Fast Implementations of Symmetric Ciphers on the Intel Pentium 4 and Beyond (Q5757698) (← links)
