PSP: parallel sub-pipelined architecture for high throughput AES on FPGA and ASIC (Q469056)
From MaRDI portal
 | This is the item page for this Wikibase entity, intended for internal use and editing purposes. Please use this page instead for the normal view: PSP: parallel sub-pipelined architecture for high throughput AES on FPGA and ASIC |
scientific article; zbMATH DE number 6367282
| Language | Label | Description | Also known as |
|---|---|---|---|
| English | PSP: parallel sub-pipelined architecture for high throughput AES on FPGA and ASIC |
scientific article; zbMATH DE number 6367282 |
Statements
PSP: parallel sub-pipelined architecture for high throughput AES on FPGA and ASIC (English)
0 references
10 November 2014
0 references
cryptography
0 references
AES
0 references
FPGA
0 references
ASIC
0 references
parallel sub-pipelined
0 references
throughput
0 references
0 references
0.86896837
0 references
0.86623806
0 references
0.8436806
0 references
