An algorithm for stuck-at fault coverage analysis of combinational and sequential logic circuits (Q1117203)
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scientific article; zbMATH DE number 4091419
| Language | Label | Description | Also known as |
|---|---|---|---|
| English | An algorithm for stuck-at fault coverage analysis of combinational and sequential logic circuits |
scientific article; zbMATH DE number 4091419 |
Statements
An algorithm for stuck-at fault coverage analysis of combinational and sequential logic circuits (English)
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1989
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An algorithm for stuck-at fault coverage analysis of digital logic circuits is presented. Based on a recently developed stuck-at fault model, the algorithm determines the effectiveness of a given test input set. The algorithm is applicable for studying sequential logic circuits, as well as combinational logic circuits. The software developed for fault coverage analysis of all single stuck-at faults is simple and fast.
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test input set
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