A methodology for algorithm regularization and mapping into time-optimal VLSI arrays (Q1208500)
From MaRDI portal
 | This is the item page for this Wikibase entity, intended for internal use and editing purposes. Please use this page instead for the normal view: A methodology for algorithm regularization and mapping into time-optimal VLSI arrays |
scientific article; zbMATH DE number 166522
| Language | Label | Description | Also known as |
|---|---|---|---|
| English | A methodology for algorithm regularization and mapping into time-optimal VLSI arrays |
scientific article; zbMATH DE number 166522 |
Statements
A methodology for algorithm regularization and mapping into time-optimal VLSI arrays (English)
0 references
16 May 1993
0 references
systolic precedence diagram
0 references
systolic directed graph
0 references
graph methodology for regularizing data flow
0 references
algorithmic transformations
0 references
systolic architecture
0 references
mapping
0 references
systolic implementation
0 references
time-optimal VLSI arrays
0 references
