CMOS realization of all-positive pinched hysteresis loops (Q1674964)
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scientific article; zbMATH DE number 6798532
| Language | Label | Description | Also known as |
|---|---|---|---|
| English | CMOS realization of all-positive pinched hysteresis loops |
scientific article; zbMATH DE number 6798532 |
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CMOS realization of all-positive pinched hysteresis loops (English)
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26 October 2017
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Summary: Two novel nonlinear circuits that exhibit an all-positive pinched hysteresis loop are proposed. These circuits employ two NMOS transistors, one of which operates in its triode region, in addition to two first-order filter sections. We show the equivalency to a charge-controlled resistance (memristance) in a decremental state via detailed analysis. Simulation and experimental results verify the proposed theory.
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nonlinear circuits
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all-positive pinched hysteresis loop
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NMOS transistors
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charge-controlled resistance (memristance)
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