Compact CMOS implementation of a low-power, current-mode programmable cellular neural network (Q2764551)

Cellular neural networks (CNN) have been studied both theoretically and in the direction of application-oriented circuit implementations, typically in image processing for more than the past ten years. The paper proposes the novel-core topology for previously proposed new CMOS full-analogy current-mode CNN by the same authors. The preliminary test-chip is designed and fabricated, consisting of the \(8\times 1\) array of fully programmable cells, with the baseline 2.5 micro CMOS technology. The simulation and experimental results are presented, which prove the correct CNN functionality. Nevertheless, it should be stressed that the test-chip presented is intended essentially as a demonstrator of the proposed new circuit technique, only. Therefore, a development of all ancillary elements which are fundamental for implementing a full functional CNN machine are left for the future.