Area-time efficient modulo 2/sup n/-1 adder design (Q4317362)
From MaRDI portal
| This is the item page for this Wikibase entity, intended for internal use and editing purposes. Please use this page instead for the normal view: Area-time efficient modulo 2/sup n/-1 adder design |
scientific article; zbMATH DE number 704060
| Language | Label | Description | Also known as |
|---|---|---|---|
| English | Area-time efficient modulo 2/sup n/-1 adder design |
scientific article; zbMATH DE number 704060 |
Statements
Area-time efficient modulo 2/sup n/-1 adder design (English)
0 references
31 January 1995
0 references
carry look-ahead adders
0 references
endaround carry adders
0 references
VLSI adders
0 references
modulo \(2^ n- 1\) adders
0 references
carry look-ahead addition algorithms
0 references
0 references
0.92063427
0 references
0.8934792
0 references
0.88924336
0 references
0.8743274
0 references