A pipelined-loop-compatible architecture and algorithm to reduce variable-length sets of floating-point data on a reconfigurable computer (Q436815)
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scientific article; zbMATH DE number 6059793
| Language | Label | Description | Also known as |
|---|---|---|---|
| English | A pipelined-loop-compatible architecture and algorithm to reduce variable-length sets of floating-point data on a reconfigurable computer |
scientific article; zbMATH DE number 6059793 |
Statements
A pipelined-loop-compatible architecture and algorithm to reduce variable-length sets of floating-point data on a reconfigurable computer (English)
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26 July 2012
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FPGA
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pipeline
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reduction
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accumulator
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sparse matrix
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iterative solver
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reconfigurable computer
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0.7091516852378845
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