A SIMULATED ANNEALING ALGORITHM FOR SYSTEM-ON-CHIP TEST SCHEDULING WITH, POWER AND PRECEDENCE CONSTRAINTS (Q5434996)
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scientific article; zbMATH DE number 5225457
| Language | Label | Description | Also known as |
|---|---|---|---|
| English | A SIMULATED ANNEALING ALGORITHM FOR SYSTEM-ON-CHIP TEST SCHEDULING WITH, POWER AND PRECEDENCE CONSTRAINTS |
scientific article; zbMATH DE number 5225457 |
Statements
A SIMULATED ANNEALING ALGORITHM FOR SYSTEM-ON-CHIP TEST SCHEDULING WITH, POWER AND PRECEDENCE CONSTRAINTS (English)
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14 January 2008
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embedded core testing
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0.8394654
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0.83810973
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0.8337307
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0.83222026
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