DCT hardware structure for sequentially presented data (Q5958658)

This paper shows that a fast discrete cosine transform (DCT) algorithm is mapped into a hardware structure that consists of \(\log_{2} N\) modules. Such a hardware structure can be used for bit-serial word-serial or word-serial bit-parallel implementation. Compared to other methods of hardware implementation, the proposed one provides a natural interface with sequentially presented input data, achieves a high utilization of hardware, requires a low processing latency and has a modular architecture that can be extended to support different transform sizes.