FPGA Implementation of Multi-Layer Machine Learning Equalizer with On-Chip Training (Q6419819)
From MaRDI portal
 | This is the item page for this Wikibase entity, intended for internal use and editing purposes. Please use this page instead for the normal view: FPGA Implementation of Multi-Layer Machine Learning Equalizer with On-Chip Training |
preprint article from arXiv
| Language | Label | Description | Also known as |
|---|---|---|---|
| English | FPGA Implementation of Multi-Layer Machine Learning Equalizer with On-Chip Training |
preprint article from arXiv |
Statements
7 December 2022
0 references
eess.SP
0 references
cs.IT
0 references
cs.LG
0 references
math.IT
0 references
stat.ML
0 references
Keren Liu
0 references
Erik Börjeson
0 references
Christian Häger
0 references
Per Larsson-Edefors
0 references
