Verification of FPGA layout generators in higher-order logic (Q877830)
From MaRDI portal
 | This is the item page for this Wikibase entity, intended for internal use and editing purposes. Please use this page instead for the normal view: Verification of FPGA layout generators in higher-order logic |
scientific article; zbMATH DE number 5149173
| Language | Label | Description | Also known as |
|---|---|---|---|
| English | Verification of FPGA layout generators in higher-order logic |
scientific article; zbMATH DE number 5149173 |
Statements
Verification of FPGA layout generators in higher-order logic (English)
0 references
3 May 2007
0 references
route algorithms
0 references
layout descriptions
0 references
