Deadline constrained cyclic scheduling on pipelined dedicated processors considering multiprocessor tasks and changeover times (Q947867)
From MaRDI portal
| This is the item page for this Wikibase entity, intended for internal use and editing purposes. Please use this page instead for the normal view: Deadline constrained cyclic scheduling on pipelined dedicated processors considering multiprocessor tasks and changeover times |
scientific article; zbMATH DE number 5349674
| Language | Label | Description | Also known as |
|---|---|---|---|
| English | Deadline constrained cyclic scheduling on pipelined dedicated processors considering multiprocessor tasks and changeover times |
scientific article; zbMATH DE number 5349674 |
Statements
Deadline constrained cyclic scheduling on pipelined dedicated processors considering multiprocessor tasks and changeover times (English)
0 references
8 October 2008
0 references
cyclic scheduling
0 references
integer linear programming
0 references
high-level synthesis
0 references
changeover times
0 references
FPGA
0 references
0 references
0.8821881
0 references
0.8755055
0 references
0.8737027
0 references
0.8675997
0 references
0.8669286
0 references
0.85753936
0 references
0.85401195
0 references
0.8518289
0 references