Complete test generation method for all stuck-at faults in combinational circuits

DOI10.1080/00207219008921209zbMATH Open0701.94020OpenAlexW1975256610MaRDI QIDQ3479983

Ugur Halici, Hasan Guran

Publication date: 1990

Published in: International Journal of Electronics (Search for Journal in Brave)

Full work available at URL: https://doi.org/10.1080/00207219008921209

zbMATH Keywords

logic gatescombinational logic circuitscomplete fault detection test setsstuck- at faults

Mathematics Subject Classification ID

Fault detection; testing in circuits and networks (94C12)

Related Items (4)

An algorithm to generate complete test sets for stuck-at faults in combinational logic circuits ⋮ Stuck-At Fault Tests in the Presence of Undetectable Bridging Faults ⋮ Title not available (Why is that?) ⋮ Title not available (Why is that?)

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