scientific article
From MaRDI portal
Publication:3688319
zbMATH Open0569.94027MaRDI QIDQ3688319
Publication date: 1984
Title of this publication is not available (Why is that?)
fault detectionmultiplierspolynomialcombinational circuitstuck-at faultaddersmulti-valued logic function
Related Items (3)
A multiple-valued logic approach to the design and verification of hardware circuits โฎ Title not available (Why is that?) โฎ Title not available (Why is that?)
Recommendations
- A multiple-valued logic approach to the design and verification of hardware circuits ๐ ๐
- Synthesizing testable combinational circuits ๐ ๐
- Easily testable multiple-valued logic circuits derived from Reed-Muller circuits ๐ ๐
- Synthesis of easily testable circuits over the basis {&, โจ, โป} for systems of Boolean functions ๐ ๐
- Synthesis of easily testable logic networks under arbitrary stuck-at faults at inputs and outputs of gates ๐ ๐
- Title not available (Why is that?) ๐ ๐
- Title not available (Why is that?) ๐ ๐
- Title not available (Why is that?) ๐ ๐
This page was built for publication:
Report a bug (only for logged in users!)Click here to report a bug for this page (MaRDI item Q3688319)