Minimum Universal Logic Module Sequential Circuits with Decoders

DOI10.1109/TC.1977.1674741zbMATH Open0365.94045OpenAlexW2084308843MaRDI QIDQ4140883

R. P. Voith

Publication date: 1977

Published in: IEEE Transactions on Computers (Search for Journal in Brave)

Full work available at URL: https://doi.org/10.1109/tc.1977.1674741

Mathematics Subject Classification ID

Formal languages and automata (68Q45)

Related Items (1)

ULM Implicants for Minimization of Univers Logic Module Circuits

Recommendations

• Logical modulo test circuits: Their design in unitary positional binary codes 👍 👎
• Complexity and synthesis of minimal logic circuits using multiplexers 👍 👎
• Minimal parallel prefix circuits 👍 👎
• Logic design of decoded-programmable logic arrays 👍 👎
• ULM Implicants for Minimization of Univers Logic Module Circuits 👍 👎
• Title not available (Why is that?) 👍 👎
• Title not available (Why is that?) 👍 👎
• Title not available (Why is that?) 👍 👎
• Title not available (Why is that?) 👍 👎

This page was built for publication: Minimum Universal Logic Module Sequential Circuits with Decoders

Report a bug (only for logged in users!)Click here to report a bug for this page (MaRDI item Q4140883)