Pages that link to "Item:Q3628468"

The following pages link to Efficient Parallel Buffer Structure and Its Management Scheme for a Robust Network-on-Chip (NoC) Architecture (Q3628468):

Displaying 7 items.

• Networks on chips -- using DQQB (Distributed queue quad-bus) on multi-CPU chips (Q419804) (← links)
• A routing-table-based adaptive and minimal routing scheme on network-on-chip architectures (Q1040943) (← links)
• Using non-preemptive regions and path modification to improve schedulability of real-time traffic over priority-based NOCs (Q1640307) (← links)
• Scalable load balancing congestion-aware Network-on-Chip router architecture (Q1953818) (← links)
• Cluster-based topologies for 3D Networks-on-Chip using advanced inter-layer bus architecture (Q1953829) (← links)
• Buffer planning for application-specific networks-on-chip design (Q2267084) (← links)
• Leaving One Slot Empty: Flit Bubble Flow Control for Torus Cache-Coherent NoCs (Q2982354) (← links)