Pages that link to "Item:Q5434996"
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The following pages link to A SIMULATED ANNEALING ALGORITHM FOR SYSTEM-ON-CHIP TEST SCHEDULING WITH, POWER AND PRECEDENCE CONSTRAINTS (Q5434996):
Displaying 2 items.
- Scheduling semiconductor multihead testers using metaheuristic techniques embedded with lot-specific and configuration-specific information (Q473662) (← links)
- Application of the simulated annealing local search technique to problems of redundancy elimination in functional and parametric tests of integrated circuits (Q1873059) (← links)