Pages that link to "Item:Q5894501"
From MaRDI portal
The following pages link to Packet mode and QoS algorithms for buffered crossbar switches with FIFO queuing (Q5894501):
Displaying 20 items.
- Online scheduling FIFO policies with admission and push-out (Q255276) (← links)
- Better bounds for online \(k\)-frame throughput maximization in network switches (Q346256) (← links)
- Competitive buffer management for multi-queue switches in QoS networks using packet buffering algorithms (Q528490) (← links)
- High-performance switching based on buffered crossbar fabrics (Q871115) (← links)
- Performance analysis of clock-regulated queues with output multiplexing in three different 2x2 crossbar switch architectures (Q1200161) (← links)
- Online packet scheduling for CIOQ and buffered crossbar switches (Q1799227) (← links)
- Combined asynchronous/synchronous packet switching architecture: QoS guarantees for integrated parallel computing and real-time traffic (Q1974674) (← links)
- Admission control in shared memory switches (Q2317132) (← links)
- The impact of processing order on performance: a taxonomy of semi-FIFO policies (Q2361355) (← links)
- Scheduling with deadlines and buffer management with processing requirements (Q2408172) (← links)
- Improved competitive performance bounds for CIOQ switches (Q2429338) (← links)
- Tight Analysis of Priority Queuing for Egress Traffic (Q2942419) (← links)
- (Q3045029) (← links)
- (Q3181440) (← links)
- Buffer Management for Packets with Processing Times (Q3452767) (← links)
- Essential Traffic Parameters for Shared Memory Switch Performance (Q3460707) (← links)
- Best Effort and Priority Queuing Policies for Buffered Crossbar Switches (Q3511396) (← links)
- FRGA Matching Algorithm in High-Speed Packet Switches (Q3628598) (← links)
- Synchronous versus asynchronous operation of a packet switch with combined input and output queueing (Q4022639) (← links)
- Best effort and priority queuing policies for buffered crossbar switches (Q5414600) (← links)