Pages that link to "Item:Q1974491"
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The following pages link to Design and implementation of a low complexity VLSI turbo-code decoder architecture for low energy mobile wireless communications (Q1974491):
Displaying 8 items.
- VLSI architectures for sliding-window-based space-time turbo Trellis code decoders (Q693833) (← links)
- Reconfigurable turbo decoding for 3G applications (Q956040) (← links)
- Memory power reduction for high-speed implementation of turbo codes (Q1405497) (← links)
- A scalable system architecture for high-throughput turbo-decoders (Q2574072) (← links)
- VLSI architecture and implementation for FS1016 CELP decoder with reduced power and memory requirements (Q3840919) (← links)
- A parallel Viterbi decoding algorithm (Q4790973) (← links)
- A Novel Low-Effort Demodulator for Low Power Short Range Wireless Transceivers (Q5008654) (← links)
- (Q5347952) (← links)
