Pages that link to "Item:Q2574072"
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The following pages link to A scalable system architecture for high-throughput turbo-decoders (Q2574072):
Displaying 4 items.
- Memory-reduced maximum a posteriori probability decoding for high-throughput parallel turbo decoders (Q318289) (← links)
- Reconfigurable turbo decoding for 3G applications (Q956040) (← links)
- Design and implementation of a low complexity VLSI turbo-code decoder architecture for low energy mobile wireless communications (Q1974491) (← links)
- Energy efficient memory architecture for high speed decoding of block turbo-codes with the Fang-Buda algorithm (Q2574076) (← links)