Pages that link to "Item:Q3934311"
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The following pages link to A Regular Layout for Parallel Adders (Q3934311):
Displaying 22 items.
- Formal proof of integer adders using all-prefix-sums operation (Q362271) (← links)
- Limited width parallel prefix circuits (Q547485) (← links)
- Formal proof of prefix adders (Q611751) (← links)
- An easily testable optimal-time VLSI-multiplier (Q1082330) (← links)
- Communication-efficient parallel algorithms for distributed random-access machines (Q1104096) (← links)
- The complexity of a VLSI adder (Q1146001) (← links)
- Computations over finite monoids and their test complexity (Q1178692) (← links)
- Mod \(m\) arithmetic in binary systems (Q1183492) (← links)
- Non-associative parallel prefix computation (Q1201872) (← links)
- Parallel prefix computation with few processors (Q1205906) (← links)
- A fully parallel algorithm for residue to binary conversion (Q1321825) (← links)
- A chained-matrices approach for parallel computation of continued fractions and its applications (Q1332396) (← links)
- Parallel evaluation of arithmetic circuits (Q1365929) (← links)
- Parallel algorithms for addition and multiplication on processor arrays with reconfigurable bus systems (Q1802064) (← links)
- A software interface and hardware design for variable-precision interval arithmetic (Q1904320) (← links)
- A novel parallel prefix adder for optimized radix-2 FFT processor (Q2044538) (← links)
- Formal verification of parallel prefix sum and stream compaction algorithms in CUDA (Q2120963) (← links)
- The applicability of discrete performance estimation methods to VLSI design (Q2366696) (← links)
- A search for Wilson primes (Q3189466) (← links)
- OPTIMAL PARALLEL PREFIX ON MESH ARCHITECTURES (Q4819965) (← links)
- Chai-Tea, Cryptographic Hardware Implementations of xTEA (Q5504636) (← links)
- Cryptanalysis of algebraic verifiable delay functions (Q6652907) (← links)
