An easily testable optimal-time VLSI-multiplier (Q1082330)

We consider the design of a 'tree-multiplier', which is a modified version of a Wallace tree-multiplier [\textit{C. S. Wallace}, IEEE Trans. Electron. Comput. EC-13, 14-17 (1964)] made suitable for VLSI-design by \textit{W. K. Luk} and \textit{J. Vuillemin} [''Recursive implementation of optimal time VLSI integer multipliers'', VLSI '83, IFIP, 155-168 (1983)]. It is shown that 4 log(n)\(+3\) test patterns suffice to exhaustively test the multiplier with respect to the 'cellular fault model' (which includes tests for all single stuck-at faults). Some slight modifications of the multiplier prove, that these tests can be applied without increasing the number of input ports substantially.