Techniques for efficiently implementing totally self-checking checkers in MOS technology (Q1101080)

This paper presents some new techniques for reducing the transistor count of MOS implementations of totally self-checking (TSC) checkers. The techniques are (1) transfer of fanouts, (2) removal of inverters and (3) use of multi-level realizations of functions. These techniques also increase the speed of the circuit and may reduce the number of required tests. Their effectiveness has been demonstrated by applying them to m- out-of-n and Berger code checkers. Impressiive reductions of up to 90 \% in the transistor count in some cases have been obtained for the MOS implementation of these checkers. This directly translates into saving of ship area.