The following pages link to Majority Gate Networks (Q5737339):
Displaying 33 items.
- Complexity of computation in finite fields (Q378003) (← links)
- An improved parallel algorithm for integer GCD (Q582082) (← links)
- Root finding with threshold circuits (Q690451) (← links)
- VLSI implementation of area-efficient truncated modified booth multiplier for signal processing applications (Q900586) (← links)
- Monotone circuits for monotone weighted threshold functions (Q1044746) (← links)
- A consideration of a practical implementation for a new convergence division (Q1055188) (← links)
- An easily testable optimal-time VLSI-multiplier (Q1082330) (← links)
- Efficient parallel circuits and algorithms for division (Q1114393) (← links)
- A design of fast pipelined modular multiplier based on a diminished-radix algorithm (Q1312101) (← links)
- Shallow circuits and concise formulae for multiple addition and multiplication (Q1312182) (← links)
- A fully parallel algorithm for residue to binary conversion (Q1321825) (← links)
- The computation of elementary functions in radix \(2^ p\) (Q1340861) (← links)
- Survey on hardware implementation of random number generators on FPGA: theory and experimental analyses (Q1706614) (← links)
- Very fast rate 2-input fuzzy processor for high energy physics (Q1867682) (← links)
- A novel parallel prefix adder for optimized radix-2 FFT processor (Q2044538) (← links)
- T-count optimized Wallace tree integer multiplier for quantum computing (Q2239664) (← links)
- Integer linear programming-based bit-level optimization for high-speed FIR decimation filter architectures (Q2269888) (← links)
- The delay of circuits whose inputs have specified arrival times (Q2370422) (← links)
- Digital equalization for cancellation of noise-like interferences in adaptive spatial filtering (Q2399053) (← links)
- Cost-efficient design of a quantum multiplier-accumulator unit (Q2411575) (← links)
- An efficient design for reversible Wallace unsigned multiplier (Q2415318) (← links)
- A quantum multiply-accumulator (Q2454263) (← links)
- Real-time arithmetic unit (Q2507549) (← links)
- Modular multiplication using the core function in the residue number system (Q2634582) (← links)
- Stability of the 7-3 compressor circuit for Wallace tree. I (Q2658811) (← links)
- Circuit level realization of low latency radix-4 Booth scheme for parallel multipliers (Q2676842) (← links)
- Design and performance analysis of LMS algorithm based adaptive filter embedded with CFAR detector under non-homogeneous clutter scenarios (Q2830847) (← links)
- Matching Multiplications in Bit-Vector Formulas (Q2961559) (← links)
- Parallel multipliers with NOR gates based on G-minimum adders (Q3676064) (← links)
- A class of systolic multiplier units for VLSI technology (Q3720474) (← links)
- Verifiable Stream Computation and Arthur--Merlin Communication (Q5232326) (← links)
- Decomposition of Boolean function and two-realizability (Q5565131) (← links)
- Cryptanalysis of algebraic verifiable delay functions (Q6652907) (← links)
