Matrix-vector multiplication on a fixed-size linear systolic array (Q1591991)
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scientific article; zbMATH DE number 1550791
| Language | Label | Description | Also known as |
|---|---|---|---|
| English | Matrix-vector multiplication on a fixed-size linear systolic array |
scientific article; zbMATH DE number 1550791 |
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Matrix-vector multiplication on a fixed-size linear systolic array (English)
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14 January 2001
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An efficient matrix-vector multiplication algorithm is presented which minimizes the execution time when implemented on the fixed size bidirectional linear systolic array (BLSA) by eliminating zero element insertions between the successive iterations. The manipulation with data transfer to/from the BLSA are handled by the memory interface subsystem (MIS). Hardware synthesis of the MIS is discussed in detail.
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matrix-vector multiplication algorithm
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bidirectional linear systolic array
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memory interface subsystem
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0.9238205
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0.9199556
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0.9165258
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