Pages that link to "Item:Q5151257"
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The following pages link to Synthesis of easily testable logic networks under arbitrary stuck-at faults at inputs and outputs of gates (Q5151257):
Displaying 12 items.
- Testable design of AND-EXOR logic networks with universal test sets (Q733292) (← links)
- Design of exclusive or sum-of-products (ESP) logic arrays with universal tests for detecting stuck-at and bridging faults (Q792959) (← links)
- The length of a single fault detection test for constant-nonpreserving element insertions (Q830998) (← links)
- An algorithm to generate complete test sets for stuck-at faults in combinational logic circuits (Q1101421) (← links)
- Testable design of two-dimensional cellular logic arrays for detecting struck-at and bridging faults (Q1119547) (← links)
- Maximum ease of testability of logic circuits with respect to multiple stuck-on faults (Q1816073) (← links)
- Short single tests for circuits with arbitrary stuck-at faults at outputs of gates (Q2332897) (← links)
- Synthesis of easily testable circuits over the Zhegalkin basis in the case of constant faults of type 0 at outputs of elements (Q3057821) (← links)
- (Q3688319) (← links)
- Synthesis of easily testable circuits over the basis {&, ∨, ⁻} for systems of Boolean functions (Q4917386) (← links)
- Short single fault detection tests for logic networks under arbitrary faults of gates (Q5071224) (← links)
- A METHOD FOR CONSTRUCTING LOGIC NETWORKS ALLOWING SHORT SINGLE DIAGNOSTIC TESTS (Q5151288) (← links)
